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1 zarlink semiconductor inc. zarlink, zl and the zarlink semiconductor logo are trademarks of zarlink semiconductor inc. copyright 1999-2005, zarlink semiconductor inc. all rights reserved. features ? receive sync output pulse ? full duplex transmission over a single twisted pair ? selectable 80 or 160 kbit/s line rate ? adaptive echo cancellation ? up to 3 km (9173) and 4 km (9174) loop reach ? isdn compatible (2b+d) data format ? transparent modem capability ? frame synchronization and clock extraction ? zarlink st-bus compatible ? low power (typically 50 mw), single 5 v supply applications ?t dd digital pcs (dect, ct2, phs) base stations requiring cell synchronization ? digital subscriber lines ? high speed data transmission over twisted wires ? digital pabx line cards and telephone sets ? 80 or 160 kbit/s single chip modem description the mt9173 (dsic) and mt9174 (dnic) are functionally identical to t he mt9171/72 except for the addition of one feature. the mt9173/74 include a digital output pin indicating the temporal position of the received "sync" bit of t he biphase transmission. this feature is especially useful for systems such as pcs wireless base station applications requiring close synchronization between microcells. the mt9173 and mt9174 are identical except for the mt9173 having a shorter loop reach. the generic "dnic" will be used to reference both devices unless otherwise noted. the mt 9173/74 are fabricated in zarlink?s iso 2 -cmos process. december 2005 ordering information mt9173ae 24 pin pdip tubes mt9173an 24 pin ssop tubes mt9173ap 28 pin plcc tubes mt9173ae1 24 pin pdip* tubes mt9173ap1 28 pin plcc* tubes MT9173AN1 24 pin ssop* tape & reel mt9174ae 24 pin pdip tubes mt9174an 24 pin ssop tubes mt9174ap 28 pin plcc tubes *pb free matte tin -40 c to +85 c iso 2 -cmos st-bus tm family mt9173/74 digital subscriber interface circuit with rxsb digital network interf ace circuit with rxsb data sheet figure 1 - functional block diagram dsti/di cdsti/ f0 /cld c4 /tck ms0 ms1 ms2 regc dsto/do cdsto/ cdo transmit interface prescrambler scrambler control register transmit/ clock receive timing & control status transmit timing master clock phase locked sync detect receive dpll receive interface de - prescrambler descrambler differentially encoded biphase receiver differentially encoded biphase transmitter transmit filter & line driver receive filter -1 +2 mux address echo canceller error signal echo estimate v bias v dd v ss v bias v ref l out l out dis precan l in osc2 osc1 ? + cdi rxsb
mt9173/74 data sheet 2 zarlink semiconductor inc. figure 2 - pin connections pin description pin # name description 24 28 12 l out line out. transmit signal output (analog). referenced to v bias . 23 v bias internal bias voltage output. connect via 0.33 f decoupling capacitor to v dd . 34 v ref internal reference voltage output. connect via 0.33 f decoupling capacitor to v dd . 4,5, 6 5,7, 8 ms2-ms0 mode select inputs (digital). the logic levels present on these pins select the various operating modes for a particular applicati on. see table 1 for the operating modes. 7 9 regc regulator control output (digital). a 512 khz clock used for switch mode power supplies. unused in mas/mod mode and should be left open circuit. 810 rxsb receive sync bit output (digital). in dn mode, this output is held high until receive synchronization occurs (i.e., until the sync bit in status register =1). once low, indicating synchronized transmi ssion, a high going pulse (6.24 s wide pulse @ 160 kb/s and 12.5 s wide @ 80 kb/s) indicates the tem poral position of the receive "sync" bit in the biphase line transmission. inactive and low in mod mode. 911f0 /cld frame pulse/c-channel load (digital). in dn mode a 244 ns wide negative pulse input for the master indicating the start of the active channel times of the device. output for the slave indicating the start of the active channel times of the device. output in mod mode providing a pulse indicating the start of the c-channel. 10 12 cdsti/ cdi control/data st-bus in/control/data in (digital). a 2.048 mbit/s serial control & signalling input in dn mode. in mod mode this is a continuous bit stream at the bit rate selected. 11 13 cdsto/ cdo control/data st-bus out/control/data out (digital). a 2.048 mbit/s serial control & signalling output in dn mode. in mod mode this is a continuous bi t stream at the bit rate selected. 12 14 v ss negative power supply (0 v). 13 15 dsto/do data st-bus out/data out (digital). a 2.048 mbit/s serial pcm/data output in dn mode. in mod mode this is a continuous bit stream at the bit rate selected. 28 pin plcc 27 4 3 2 1 28 26 5 6 7 8 9 10 11 25 24 23 22 21 20 19 17 12 13 14 15 16 18 2 lout vbias vref nc vdd lin test nc lout dis precan osc1 osc2 nc c4 /tck ms2 nc ms1 ms0 regc f0 /cld cdsti/cdi cdsto/cdo vss dsto/do nc f0o /rck dsti/di 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 24 23 22 21 20 19 18 17 24 pin pdip/ ssop lout vbias vref ms2 ms1 ms0 regc f0 /cld cdsti/cdi cdsto/cdo vss rxsb vdd lin test lout dis precan osc1 osc2 c4 /tck f0o /rck dsti/di dsto/do nc rxsb
mt9173/74 data sheet 3 zarlink semiconductor inc. figure 3 - dv port - 80 kbit/s (modes 2, 3, 6) 14 16 dsti/di data st-bus in/data in (digital). a 2.048 mbit/s serial pcm/data input in dn mode. in mod mode this is a continuous bi t stream at the bit rate selected. 15 17 f0o /rck frame pulse out/receive bit rate clock output (digital). in dn mode a 244 ns wide negative pulse indicating the end of t he active channel times of the device to allow daisy chaining. in mod mode provides th e receive bit rate clock to the system. 16 19 c4 /tck data clock/transmit baud rate clock (digital). a 4.096 mhz ttl compatible clock input for the master and output for the sl ave in dn mode. for mod mode this pin provides the transmit bit rate clock to the system. 17 21 osc2 oscillator output . cmos output. 19 22 osc1 oscillator input . cmos input. d.c. couple signals to this pin. refer to d.c. electrical characteristics for os c1 input requirements. 20 23 precan precanceller disable. when held to logic ?1? , the internal path from l out to the precanceller is forced to v bias thus bypassing the precancelle r section. when logic ?0?, the l out to the precanceller path is enabled and functions normally. an internal pulldown (50 k ? ) is provided on this pin. 18 1,6, 18, 20, 25 nc no connection. leave open circuit 21 24 l out dis l out disable. when held to logic ?1?, l out is disabled (i.e., output = v bias ). when logic ?0?, l out functions normally. an internal pulldown (50 k ? ) is provided on this pin. 22 26 test test pin. connect to v ss . 23 27 l in receive signal input (analog). 24 28 v dd positive power supply (+5 v) input. pin description (continued) pin # name description 24 28 f0 c4 dsti dsto f0o b1 7 b1 6 b1 5 b1 4 b1 3 b1 2 b1 1 b1 0 b1 7 b1 6 b1 5 b1 4 b1 3 b1 2 b1 1 b1 0 b1 7 b1 7 channel time 0
mt9173/74 data sheet 4 zarlink semiconductor inc. figure 4 - dv port - 160 kbit/s (modes 2, 3, 6) functional description the mt9173 and mt9174 are multifunction devices capable of providing high speed, full duplex digital transmission at up to 160 kbit/s over a twisted wire pair. they us e adaptive echo-cancelling techniques and transfer data in a format compatible to the isdn basic rate. several m odes of operation allow an easy interface to digital telecommunication networks including pcs wireless base stations, smart telephone sets, workstations, data terminals and computers. the device supports the 2b+d channel format (two 64 kbit/s b-channels and one 16 kbit/s d-channel) over two wires as recommended by the ccitt. the line data is converted to and from the st- bus format on the system side of th e network to allow for easy interfacin g with other components such as the s- interface device in an nt1 arrangem ent, or to digital pabx components. smart telephone sets with data and voice capability can be easily implemented using the mt9173/74 as a line interface. the device?s high bandwidth and long loop length capability allows its use in a wide variety of sets. this can be extended to provide full data and voice capability to the private subscriber by the installation of equipment in both the home and central office or remote concentra tion equipment. within the subscriber equipment the mt9173/74 would terminate the line and encode/ decode the data and voice for transmission while additional electronics could provide interfaces for a standard tel ephone set and any number of data ports supporting standard data rates for such things as computer communications and telemetry for remote meter reading. digital workstations with a high degree of networking capability can be designed us ing the dnic for the line interface, offering up to 160 kbit/s data transmission over exis ting telephone lines. the mt9 173/74 could also be valuable within existing computer networks for connecting a large number of terminals to a computer or for intercomputer links. with the dnic, this can be accomplished at up to 16 0 kbit/s at a very low cost per line for terminal to computer links and in many cases this bandwidth wo uld be sufficient for computer to computer links. figure 1 shows the block diagram of the mt9173/74. t he dnic provides a bidirecti onal interface between the dv (data/voice) port and a full dupl ex line operating at 80 or 160 kbit/s over a single pair of twisted wires. the dnic has three serial ports. the dv port (dsti/di, dsto/do), th e cd (control/data) port (cdsti/cdi, cdsto/cdo) and a line port (l in , l out ). the data on the line is made up of information from the dv and cd ports. the dnic must combine information received from both the dv and cd ports and put it onto the line. at the same time, the data received from the line must be split into the various channels and directed to the proper ports. the usable data rates are 72 f0 c4 dsti dsto f0o b1 7 b1 6 b1 5 b1 4 b1 3 b1 2 b1 1 b1 0 b1 7 b1 7 channel time 0 b1 7 b1 6 b1 5 b1 4 b1 3 b1 2 b1 1 b1 0 b2 7 b2 6 b2 5 b2 4 b2 3 b2 2 b2 1 b2 0 b2 7 b2 6 b2 5 b2 4 b2 3 b2 2 b2 1 b2 0 channel time 16
mt9173/74 data sheet 5 zarlink semiconductor inc. and 144 kbit/s as required for the basic rate interface in isdn. full duplex transmission is made possible through on board adaptive echo cancellation. the dnic has various modes of operation which are selected through the mode select pins ms0-2. the two major modes of operation are the modem (mod) and digital network (dn) mo des. mod mode is a transparent 80 or 160 kbit/s modem. in dn mode the line carries the b and d channels formatted for the isdn at either 80 or 160 kbit/s. in the dn mode the dv and cd ports are standard st-bus and in mod mode they are transparent serial data streams at 80 or 160 kbit/s. other modes in clude: master (mas) or slave (slv) mode, where the timebase and frame synchronization are provided externally or are extrac ted from the line and dual or single (singl) port modes, where both the dv and cd ports ar e active or where the cd port is inactive and all information is passed through the dv port. for a detailed description of the modes see ?operating modes? section. in digital network (dn) mode there are three channels tr ansferred by the dv and cd ports. they are the b, c and d channels. the b1 and b2 channels each have a bandwidth of 64 kbit/s and are used for carrying pcm encoded voice or data. these channels are always transmit ted and received through the dv port (figures 3, 4, 5, 6). the c-channel, having a bandwidth of 64 kbit/s, provides a means for the system to control the dnic and for the dnic to pass status information back to the system. th e c-channel has a housekeeping (hk) bit which is the only bit of the c-channel transmitted and received on the li ne. the 2b+d channel bits and the hk bit are double- buffered. the d-channel can be transmitt ed or received on the line with either an 8, 16 or 64 kbit/s bandwidth depending on the dnic?s mode of operation. both the hk bit and the d-channel can be used for end-to-end signalling or low speed data transfer. in dual port mode the c and d channels are accessed via the cd port (figure 7) while in singl port mode t hey are transferred through the dv port (f igures 5, 6) along with the b1 and b2 channels. figure 5 - dv port - 80 kbit/s (modes 0,4) figure 6 - dv port - 160 kbit/s (modes 0,4) channel time 0 d-channel channel time 1 c-channel channel time 2 b1-channel 11.7 sec f0 c4 dsto dsti f0o d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 c 0 c 1 c 2 c 3 c 4 c 5 c 6 c 7 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 c 0 c 1 c 2 c 3 c 4 c 5 c 6 c 7 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 d 0 d 0 channel time 0 d-channel channel time 1 c-channel channel time 2 b1-channel 15.6 sec f0 c4 dsto dsti f0o d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 c 0 c 1 c 2 c 3 c 4 c 5 c 6 c 7 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 c 0 c 1 c 2 c 3 c 4 c 5 c 6 c 7 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 d 0 d 0 channel time 3 b2-channel b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0
mt9173/74 data sheet 6 zarlink semiconductor inc. figure 7 - cd port (modes 2,6) figure 8 - cd port (modes 1,5) in digital network (dn) mode, upon entering the dni c from the dv and cd ports, the b-channel data, d- channel d0 (and d1 for 160 kbit/s), the hk bit of the c- channel (160 kbit/s only) and a sync bit are combined in a serial format to be sent out on the line by the trans mit interface (figures 11, 12). the sync bit produces an alternating 1-0 pattern each frame in order for the remote end to extract the frame alignment from the line. it is possible for the remote end to lock on to a data bit pattern wh ich simulates this alternating 1-0 pattern that is not the true sync. to decrease the probabilit y of this happening the dnic may be programmed to put the data through a prescrambler that scrambles the data according to a predetermined polynomial with respect to the sync bit. this greatly decreases the probab ility that the sync pattern ca n be reproduced by any data on the line. in order for the echo canceller to function correctly, a dedicated scrambler is used with a scrambling algorithm which is different for the slv and mas modes. these algorithm s are calculated in such a way as to provide orthogonality between the near and far end data streams such that the co rrelation between the two signals is very low. for any two dnics on a link, one must be in slv mode with the other in mas mode. the scrambled data is differentially encoded which serves to make the data on the line polarity-independent. it is then biphase encoded as shown in figure 10. see ?line interfac e? section for more details on the encoding. before leaving the dnic the differentially encoded biphase data is passed through a puls e-shaping bandpass transmit filter that filters out the high and low frequency components and conditions the signal for transmission on the line. f0 c4 cdsto cdsti f0o c 0 c 1 c 2 c 3 c 4 c 5 c 6 c 7 c 0 c 1 c 2 c 3 c 4 c 5 c 6 c 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 c 0 c 0 3.9 sec 62.5 sec 125 sec channel time 0 channel time 16 cld tck cdi cdo c 0 c 1 c 2 c 3 c 4 c 5 c 6 c 7 c 6 c 7 c 0 c 1 c 0 c 1 c 2 c 3 c 4 c 5 c 6 c 7 c 6 c 7 c 0 c 1
mt9173/74 data sheet 7 zarlink semiconductor inc. the composite transmit and receive signal is received at l in . on entering the dnic this signal passes through a precanceller which is a summing amplifier and lowpass filter that partially cancels the near-end signal and provides first order antialiasing for the received si gnal. internal, partial cancellation of th e near end signal may be disabled by holding the precan pin high. this mode simplifies the design of external li ne transceivers used for loop extension applications. the precan pin features an internal pull-down which allows this pin to be left unconnected in applications where this function is not required. the resultant signal passes th rough a receive filter to bandlimit and equalize it. at this point, the echo estimate from the echo canceller is subtracted from the precancelled received signal. this difference signal is then input to the ec ho canceller as an error signal and also squared up by a comparator and passed to the biphase receiver. within the echo canceller, the sign of this error signal is determined. depending on the sign, the echo estimate is either incremented or decremented and this new estimate is stored back in ram. the timebase in both slv and mas modes (generated internally in slv mode and externally in mas mode) is phase-locked to the received data stream. this phase-lo cked clock operates the biphase decoder, descrambler and deprescrambler in mas mode and the entire chip in slv mode. the biphase decoder decodes the received encoded bit stream resulting in the original nrz data which is passed onto the descrambler and deprescrambler where the data is restored to its original content by performing the reverse polynomials. the sync bits are extracted and the receive interface separates the channels and outputs them to the proper ports in the proper channel times. the destination of the various channels is t he same as that received on the input dv and cd ports.
mt9173/74 data sheet 8 zarlink semiconductor inc. the transmit/receive timing and control block generates all the clocks for the transmit and receive functions and controls the entire chip according to the control register . in order that more than one dnic may be connected to the same dv and cd ports an f0o signal is generated which signals the next device in a daisy chain that its channel times are now active. in this arrangement only the first dnic in the chain receives the system f0 with the following devices receiving its predecessor?s f0o . in mod mode, all the ports have a different format. the li ne port again operates at 80 or 160 kbit/s, however, there is no synchronization overhead, only tr ansparent data. the dv and cd ports carry serial data at 80 or 160 kbit/s with the dv port transferring all the data for the line and the cd port carrying the c-channel only. in this mode the transfer of data at both port s is synchronized to the tck and rck clocks for transmit and rece ive data, respectively. the cld signal goes low to indicate the star t of the c-channel data on the cd port. it is used to load and latch the input and output c-channel but has no re lationship to the data on the dv port. in dn mas mode, the rxsb pin outputs a pulse corresponding to the position of the sync hronization bit within the received biphase data stream. since the delay in transmi ssion between dnics is dependent upon line length, the position of the rxsb pulse will vary as the line length is varied. this feat ure can be used to determine total loop delay which is necessary in wireless base stations where all of the microcells need to be synchronized. in dn slv mode, the rxsb pin is also active although its timing is fi xed and does not vary with line length. for both dn mas and slv modes, the rxsb pin can be also used as a hardware sync indicator. in modem mode, for both mas and slv ends, the rxsb pin is inactive and held low. operating modes (ms0-2) the logic levels present on the mode select pins ms0, ms1 and ms2 program the dnic for different operating modes and configure the dv and cd ports accordingly. table 1 shows the modes corresponding to the state of ms0-2. these pins select the dnic to operate as a mast er or slave, in dual or single port operation, in modem or digital network mode and the order of the c and d channels on the cd port. table 2 provides a description of each mode and table 3 gi ves a pin configuration according to t he mode selected for all pins that have variable functions. these functions vary depending on whet her it is in mas or slv, and whether dn or mod mode is used. table 1 - mode select pins e=enabled x=not applicable blanks are disabled mode select pins mode operating mode ms2 ms1 ms0 slv mas dual singl mod dn d-c c-d ode 00 0 0 e e e e e 00 1 1 e e e x x e 01 0 2 e e e e e 01 1 3 e e e e e 10 0 4 e e e e e 10 1 5 e e e x x e 11 0 6 e e e e e 11 1 7 e e e e
mt9173/74 data sheet 9 zarlink semiconductor inc. table 2 - mode definitions table 3 - pin configurations mode function slv slave - the chip timebase is extracted from the re ceived line data and the external 10.24 mhz crystal is phase locked to it to provide clocks fo r the entire device and are output for the external system to synchronize to. mas master - the timebase is derived from the externally supplied data clocks and 10.24 mhz clock which must be frequency locked. the transmit data is synchronized to the system timing with the receive data recovered by a clock extracted from the receive data and resynchronized to the system timing. dual dual port - both the cd and dv ports are active with the cd port transferri ng the c&d channels and the dv port transferring the b1& b2 channels. singl single port - the b1& b2, c and d channels are all transf erred through the dv port. the cd port is disabled and cdsti should be pulled high. mod modem - baseband operation at 80 or 160 kbits/s. the line data is received and transmitted through the dv port at the baud rate selected. t he c-channel is transferred through the cd port also at the baud rate and is synchronized to the cld output. dn digital network - intended for use in the digital network with the dv and cd ports operating at 2.048 mbits/s and the line at 80 or 160 kbits/s configured according to the applicable isdn recommendation. d-c d before c-channel - the d-channel is transferred be fore the c-channel following f0 . c-d c before d-channel - the c-channel is transferred be fore the d-channel following f0 . ode output data enable - when mode 7 is selected, the dv and cd ports are put in high impedance state. this is intended for power-up reset to avoid bus contention and possible damage to the device during the initial random state in a daisy chai n configuration of dnics. in all the other modes of operation dv and cd ports are enabled during the appropriate channel times. mode # f0 /cld f0o /rck c4 /tck name input/output name input/output name input/output 0f0 input f0o output c4 input 1cld output rck output tck output 2f0 input f0o output c4 input 3f0 input f0o output c4 input 4f0 output f0o output c4 output 5cld output rck output tck output 6f0 output f0o output c4 output 7f0 input f0o output c4 input
mt9173/74 data sheet 10 zarlink semiconductor inc. the overall mode of operation of the dnic can be progr ammed to be either a baseband modem (mod mode) or a digital network transceiver (dn mode). as a baseband modem, transmit/receive data is passed transparently through the device at 80 or 160 kbit/s by the dv port. the cd port transfers the c-cha nnel and d-channel also at 80 or 160 kbit/s. in dn mode, both the dv and cd ports operate as st-bus streams at 2.048 mbit/s. t he dv port transfers data over pins dsti and dsto while on the cd port, the cdsti and cdsto pins are used. the singl port option only exists in dn mode. in mod mode, dual port operation must be used and the d, b1 and b2 channel designations no longer exist. the selection of slv or mas will determine which of the dn ics is using the externally supplied clock and which is phase locking to the data on the line. due to jitter and end to end delay, one end must be the master to generate all the timing for the link and the other must extract the timing from the receive data and synchronize itself to this timing in order to recover the synchronous data. dual port mode a llows the user to use two separate serial busses: the dv port for pcm/data (b channels) and the cd port for cont rol and signalling information (c and d channels). in the singl port mode, all four channels are concatenated into one serial stream and input to the dnic via the dv port. the order of the c and d channels may be changed on ly in dn/dual mode. the dnic may be configured to transfer the d-channel in channel 0 a nd the c-channel in channel 16 or vice versa. one other feature exists; ode, where both the dv and cd ports are tristated in order that no devices are damaged due to excessive loading while all dnics are in a random state on power up in a daisy chain arrangement. dv port (dsti/di, dsto/do) the dv port transfers data or pcm encoded voice to and from the line according to the particular mode selected by the mode select pins. the modes affect ing the configuration of the dv port are mod or dn and dual or singl. in dn mode the dv port operates as an st-b us at 2.048 mbit/s with 32, 8 bit channels per frame as shown in figure 9. in this mode the dv port channel configuration depends upon whether dual or singl port is selected. when dual port mode is used, the c and d channels are passe d through the cd port and the b1 and b2 channels are passed through the dv port. at 80 kbit/s only one channel of the avail able 32 at the dv port is utilized, this being channel 0 which carries the b1-channel. this is shown in figure 3. at 160 kbit/s, tw o channels are used, these being 0 and 16 carrying the b1 and b2 channels, respective ly. this is shown in figure 4. when singl port mode is used, channels b1, b2, c and d are all passed via the dv por t and the cd port is disabl ed. see cd port description for an explanation of the c and d channels. figure 9 - st-bus format the d-channel is always passed during channel time 0 follo wed by the c and b1 channels in channel times 1 and 2, respectively for 80 kbit/s. see figure 5. for 160 kbit/ s the b2 channel is added and occupies channel time 3 of the dv port. see figure 6. for all of the various configur ations the bit orders are shown by the respective diagram. in mod mode the dv and cd ports no longer operate at 2.048 mbits/s but are cont inuous serial bit streams operating at the bit rate selected of 80 or 160 kbit/s. wh ile in the mod mode only dual port operation can be used. channel 0 channel 1 channel 2 ? ? ? ? ? ? ? ? bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 125 sec channel 31 channel 30 channel 31 channel 0 channel 29 f0 st-bus most significant bit (first) least significant bit (last) 3.9 sec
mt9173/74 data sheet 11 zarlink semiconductor inc. in order for more than one dnic to be connected to any one dv and cd port, making more efficient use of the busses, the dsto and cdsto outputs are put into high im pedance during the inactive channel times of the dnic. this allows additional dnics to be cascaded onto the same dv and cd ports. when used in this way a signal called f0o is used as an indication to the next dnic in a daisy chain that its channel time is now active. only the first dnic in the chain receives t he system frame pulse and all others receive the f0o from its predecessor in the chain. this allows up to 16 dnics to be cascaded. cd port (cdsti/cdi, cdsto/cdo) the cd port is a serial bidire ctional port used only in dual po rt mode. it is a means by which the dnic receives its control information for things such as setting the bi t rate, enabling internal loopback tests, sending status information back to the system and transferring low speed signalling data to and from the line. the cd port is composed of the c and d-channels. the c-channel is used for transferring control and status information between the dni c and the system. the d- channel is used for sendi ng and receiving signalling information and lower speed data between the line and the system. in dn/dual mode the dnic receives a c- channel on cdsti while transmitting a c-channel on cdsto. f ifteen channel times later (halfway through the frame) a d-channel is received on cdsti while a d-channel is transmitted on cdsto. this is shown in figure 7. the order of the c and d bytes in dual port mode can be reversed by the mode select pins. see table 1 for a listing of the byte orientations. the d-channel exists only in dn mode and may be used for transferring low speed dat a or signalling information over the line at 8, 16 or 64 kbit/s (by using the dinb feature). the inform ation passes transparently through the dnic and is transmitted to or received from the line at the bit rate selected in the control register. if the bit rate is 80 kbit/s, only d0 is transmitted and received. at 160 kbit/s, d0 and d1 are transmitted and received. when the dinb bit is set in the control regist er the entire d-channel is transmitted and received in the b1-channel timeslot. the c-channel is used for transferring control and st atus information between the dnic and the system. the control and diagnostics registers are accessed through the c-channel. they contain information to control the dnic and carry out the diagnostics as well as the hk bit to be transmitted on the line as described in tables 4 and 5. bits 0 and 1 of the c-channel select between the control and diagnostics regi ster. if these bits are 0, 0 then the c-channel information is written to the control register (table 4) . if they are 0, 1 the c- c hannel is written to the diagnostics register (table 5).
mt9173/74 data sheet 12 zarlink semiconductor inc. table 4 - control register note 1: suggested use of attack: - at 160 kbit/s full convergence requires 850 ms with attack held high for the first 240 frames or 30 ms. -at 80 kbit/s full convergence requires 1.75 s with attack held high for the first 480 frames or 60 ms. note 2: when bits 4-7 of the control register are all set to one, the dnic operates in one of the default modes as defined in ta ble 4a, depending upon the status of bit-3. table 4a. default mode selection note 3: default mode 1 can also be selected by tying cdsti/cdi pin low when dnic is operating in dual mode. note 4: default mode 2 can also be selected by tying cdsti/cdi pin high when dnic is operating in dual mode. bit name description 0 reg sel-1 register select-1. must be se t to?0? to select the control register. 1 reg sel-2 register select-2. must be se t to?0? to select the control register. 2 drr diagnostics register reset. writing a "0" to this bit will ca use a diagnostics register reset to occur coincident with the next frame pulse as in the mt8972a. when this bit is a logic "1", the diagnos tics register will not be reset. 3 brs bit rate select. when set to ?0? selects 80 kbit/s. when set to ?1?, selects 160 kbit/s. 4dinb 2 d-channel in b timeslot. when ?0?, the d-c hannel bits (d0 or d0 and d1) corresponding to the selected bit rate (80 or 160 kbit/s) are transmitted during the normal d-channel bit times. when set to ?1?, the entire d-channel (d0-d7) is transmitted during the b1-channel timeslot on the line providing a 64 kbit/s d-channel link. 5 psen 2 prescrambler/deprescrambler enable. when set to ?1?, the dat a prescrambler and deprescrambler are enabled. when set to ?0?, the data prescrambler and deprescrambler are disabled. 6attack 2 convergence speedup. when set to ?1?, the echo canceller will converge to th e reflection coefficient much faster. used on power-up for fast convergence. 1 when ?0?, the echo canceller will require the nor mal amount of time to converge to a reflection coefficient. 7txhk 2 transmit housekeeping. when set to ?0?, logi c zero is transmitted over the line as housekeeping bit. when set to ?1?, lo gic one is transmitted over the line as housekeeping bit. c-channel (bit 0-7) internal control register internal diagnostic register description xxx01111 00000000 01000000 default mode-1 3 : bit rate is 80 kbit/s. attack, psen, dinb, drr and all diagnostics are disabled. txhk=0. xxx11111 00010000 01000000 default mode-2 4 bit rate is 160 kbit/s. attack, psen, dinb, drr and all diagnostics are disabled. txhk=0. bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 reg sel-1 reg sel-2 drr brs dinb psen attack txhk default mode selection (refer to table 4a)
mt9173/74 data sheet 13 zarlink semiconductor inc. table 5 - diagnostic register note 1: when bits 4-7 of the diagnostic register are all set to one, the dnic operates in one of the default modes as defined in table 4a, depending upon the status of bit-3. note 2: do not use l out to l in loopback in dn/slv mode. note 3: do not use dsto to dsti loopback in mod/mas mode. the diagnostics register reset bit (bit 2) of the contro l register determines the re set state of the diagnostics register. if, on writing to the control r egister, this bit is set to logic ?0?, the diagnostics register will be reset coincident with the frame pulse. when this bit is logic ?1?, t he diagnostics register will not be reset. in order to use the diagnostic features, the diagnostics register must be continuously written to. the output c-channel sends status information from the status register to the s ystem along with the received hk bit as shown in table 6. in mod mode, the cd port is no longer an st-bus but is a serial bit stream operating at the bit rate selected. it continues to transfer the c-channel but the d-channel and the hk bit no l onger exist. dual port operation must be used in mod mode. the c-channel is cloc ked in and out of the cd port by tck and cld with tck defining the bits and cld the channel boundaries of the data stream as shown in figure 8. bit name description 0 reg sel-1 register select-1. must be set to ?0? to select the diagnostic register. 1 reg sel-2 register select-2. must be set to ?1? to select the diagnostic register. 2,3 loopback bit 2 bit 3 0 0 all loopback testing function s disabled. normal operation. 0 1 dsti internally looped back into dsto for system diagnostics. 10l out is internally looped back into l in for system diagnostics. 2 1 1 dsto is internally looped back into dsti for end-to-end testing. 3 4fun 1 force unsync. when set to ?1?, the dnic is forced out-of-sync to test the sync recovery circuitry. when set to ?0?, t he operation continues in synchronization. 5 pswap 1 polynomial swap. when set to ?1?, the scrambling and descrambling polynomials are interchanged (use for mas mode only). when set to ?0?, the polynomials retain their normal designations. 6dlo 1 disable line out. when set to ?1?, the signal on l out is set to v bias . when set to ?0?, l out pin functions normally. 7 not used must be set to ?0? for normal operation. bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 reg sel-1 reg sel-2 loopback fun pswap dlo not used default mode selection (refer to table 4a)
mt9173/74 data sheet 14 zarlink semiconductor inc. line port (l in , l out ) the line interface is made up of l out and l in with l out driving the transmit signal onto the line and l in receiving the composite transmit and receive signal from the line. the line code used in the dnic is biphase and is shown in figure 10. the scrambled nrz data is differentially encoded meaning the prev ious differential encoded output is xor?d with the current data bit which produces the current output. this is then biphas e encoded where transitions occur midway through the bit cell with a negative going transition indicating a logi c "0" and a positive going transition indicating a logic "1". there are some major reasons for using a biphase line code. the power density is concentrated in a spectral region that minimizes dispersion and di fferential attenuation. this can shor ten the line response and reduce the intersymbol interference which are crit ical for adaptive echo cancellation. th ere are regular zero crossings halfway through every bit cell or baud which allows simple clock ex traction at the receiving end. there is no d.c. content in the code so that phantom power feed may be applied to the line and simple transformer coupling may be used with no effect on the data. it is bipolar, ma king data reception simple and providin g a high signal to noise ratio. the signal is then passed through a bandpass filter which cond itions the signal for the li ne by limiting the spectral content from 0.2f baud to 1.6f baud and on to a line driver where it is made available to be put onto the line biased at v bias . the resulting transmit signal will have a distributed spectrum with a peak at 3/4f baud . the transmit signal (l out ) may be disabled by holding the l out dis pin high or by writing dlo (b it 6) of the diagnostics register to logic ?1?. when disabled, l out is forced to the v bias level. l out dis has an internal pull-down to allow this pin to be left not connected in applications where this function is not required. the receive signal is the above transmit signal superimposed on the signal from the remote end and an y reflections or delayed sym bols of the near end signal. the frame format of the transmit data on the line is shown in figures 11 and 12 for the dn mode at 80 and 160 kbit/s. at 80 kbit/s a sync bit for frame recovery, one bit of the d-channel and the b1-channel are transmitted. at 160 kbit/s a sync bit, the hk bi t, two bits of the d-channel and both b1 and b2 channels are transmitted. if the dinb bit of the control register is set, the entire d-channel is transmitted during the b1-channel timeslot. in mod mode the sync, hk and d-channel bits are not transmitt ed or received but rather a continuous data stream at 80 or 160 kbit/s is present. no frame recovery information is present on the line in mod mode. table 6 - status register status register name function 0 sync synchronization - when set this bit indicates that synchronization to the received line data sync pattern has been acquired. for dn mode only. 1-2 chqual channel quality - these bits provide an estimate of the receiver?s margin against noise. the farther this 2 bit value is from 0 the better the snr. 3 rx hk housekeeping - this bit is the received housekeeping (hk) bit from the far end. 4-6 future future functionality. these bits return logic 1 when read. 7 id this bit provides a hardware identifier fo r the dnic revision. the mt9173/74 will return a logic ?0? for this bit. 01234567 sync chqual rx hk future functionality id
mt9173/74 data sheet 15 zarlink semiconductor inc. figure 10 - data & line encoding figure 11 - frame format - 80 kbit/s (modes 0, 2, 3, 4, 6) figure 12 - frame format - 160 kbit/s (modes 0, 2, 3, 4, 6) bits data nrz data differential encoded differential encoded biphase transmit line signal bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 11100100 v bias note: last bit sent was a logic 0 f0 l out b1 7 sync d 0 b1 0 b1 1 b1 2 b1 3 b1 4 b1 5 b1 6 b1 7 sync f0 l out sync hk0 d 1 d 0 b 1 0 b 1 1 b 1 2 b 1 3 b 1 4 b 1 5 b 1 6 b 1 7 b 2 0 b 2 1 b 2 2 b 2 3 b 2 4 b 2 5 b 2 6 b 2 7 sync
mt9173/74 data sheet 16 zarlink semiconductor inc. applications typical connection diagrams are show n in figures 13 and 14 for the dn mode as a master and slave, respectively. l out is connected to the coupling transformer thr ough a resistor r2 and capacitors c2 and c2? to match the line characteristic impedance. suggested values of r2, c2 and c2? for 80 and 160 kbit/s operation are provided in figures 13 and 14. overvoltage protection is pr ovided by r1, d1 and d2. c1 is present to properly bias the received line signal for the l in input. a 2:1 coupling transformer is used to couple to the line with a secondary center tap for optional phantom power f eed. varistors have been shown for sur ge protection against such things as lightning strikes. if the scramblers power up with all zeros in them, they ar e not capable of randomizing all-zeros data sequence. this increases the correlation between the transmit and receive data which may cause loss of convergence in the echo canceller and high bit error rates. in dn mode the insertion of the sync pattern will provide enough pseudo-random activity to maintain convergence. in mod mode the sync pattern is not inserted. for this reason, at least on ?1? must be fed into the dnic on power up to ensure that the scramblers will randomize any subsequen t all-zeros sequence. figure 13 - typical connection diagram - mas/dn mode, 160 kbit/s dv port st-bus cd port st-bus master clocks mode select lines { { { +5 v 0.33 f 0.33 f dsti dsto cdsti cdsto f0 c4 ms0 ms1 ms2 v ref v bias l out l in osc1 osc2 f0o nc d.c. coupled, frequency locked 10.24 mhz clock. r2 = 390 ? r1 = 47 ? c2? = 1.5 nf c2 = 22 nf +5 v d1 = d2 = mur405 d2 2 : 1 1.0 f line feed voltage for 80 kbit/s: c2? = 3.3 nf c1 = 0.33 f 68 volts (typ) 2.5 joules 0.02 watt note: low leakage diodes (1 & 2) are required so that the dc voltage at l in av bias to next dnic mt9173/74 characteristics dn mode. clock timing refer to ac electrical rxsb to time measurement circuitry
mt9173/74 data sheet 17 zarlink semiconductor inc. figure 14 - typical connection diagram - slv/dn mode, 160 kbit/s ** exceeding these values may cause permanent damage. functional operation under these conditions is not implied. * typical figures are at 25 c and are for design aid only: not guaranteed and not subject to production testing. ? parameters over recommended temperature & power supply voltage ranges. absolute maximum ratings ** - voltages are with respect to ground (v ss ) unless otherwise stated. parameter symbol min. max. units 1 supply voltage v dd -0.3 7 v 2 voltage on any pin (other than supply) v max -0.3 v dd +0.3 v 3 current on any pin (other than supply) i max 40 ma 4 storage temperature t st -65 +150 c 5 package power dissipation (derate 16mw/ c above 75 c) p diss 750 mw recommended operating conditions ? - voltages are with respect to ground (v ss ) unless otherwise stated. characteristics sym. min. typ.* max. units test conditions 1 operating supply voltage v dd 4.75 5.00 5.25 v 2 operating temperature t op -40 +85 c 3 input high voltage (except osc1) v ih 2.4 v dd v for 400 mv noise margin 4 input low voltage (except osc1) v il 0 0.4 v for 400 mv noise margin dv port st-bus cd port st-bus master clocks mode select lines +5 v 0.33 f 0.33 f dsti dsto cdsti cdsto f0 c4 ms0 ms1 ms2 v ref v bias l out l in osc1 osc2 r2 = 390 ? r1 = 47 ? c2? = 1.5 nf c2 = 22 nf +5 v d1 = d2 = mur405 d2 2:1 { { { 1.0 f for 80 kbit/s: c2? = 3.3 nf c1 = 0.33 f 68 volts (typ) 0.02 watt note: low leakage diodes (1 & 2) are required so 2.5 joules that the dc voltage at l in av bias 10.24 mhz xtal c3=33 pf=c4 supply mt9173/74 rxsb to hardware sync indicator (optional)
mt9173/74 data sheet 18 zarlink semiconductor inc. * typical figures are at 25 c and are for design aid only: not guaranteed and not subject to production testing. ? parameters over recommended temperature & power supply voltage ranges. dc electrical characteristics ? - voltages are with respect to ground (v ss ) unless otherwise stated. characteristics sym. min. typ. * max. units test conditions 1 o u t p u t s operating supply current i dd 10 ma 2 output high voltage (ex osc2) v oh 2.4 v i oh =10 ma 3 output high current (except osc2) i oh 10 ma source current. v oh =2.4 v 4 output high current - osc2 i oh 10 ma source current v oh =3.5 v 5 output low voltage (ex osc2) v ol 0.4 v i ol =5 ma 6 output low current (except osc2) i ol 5 7.5 ma sink current. v ol =0.4 v 7 output low current - osc2 i ol 10 ma sink current. v ol =1.5 v 8 high imped. output leakage i oz 10 ma v in =v ss to v dd 9 output voltage (v ref ) (v bias ) v o v bias - 1.8 v dd /2 v v 10 11 i n p u t s input high voltage (ex osc1) v ih 2.0 v 12 input low voltage (ex osc1) v il 0.8 v 13 input high voltage (osc1) v iho 4.0 v 14 input low voltage (osc1) v ilo 1.0 v 15 input leakage current i il 10 ma v in =v ss to v dd 16 input pulldown impedance l out dis and precan z pd 50 k ? 17 input leakage current for osc1 input i iosc 20 ma
mt9173/74 data sheet 19 zarlink semiconductor inc. ? timing is over recommended temperature & power supply voltages. * typical figures are at 25 c and are for design aid only: not guaranteed and not subject to production testing. note 1: duty cycle is measured at v dd /2 volts. . ? timing is over recommended temperature & power supply voltages. * typical figures are at 25 c and are for design aid only: not guaranteed and not subject to production testing. note 1: when operating as a slave the c4 clock has a 40% duty cycle. note 2: when operating in mas/dn mode, the c4 and oscillator clocks must be ex ternally frequen cy-locked (i.e., f c =2.5xf c4 ). the relative phase between these two clocks ( in fig. 17) is not critical and may vary from 0 ns to t c4p . however, the relative jitter must be less than j c (see figure 17). figure 15 - c4 clock & frame pulse alignment for st-bus streams ac electrical characteristics ? - voltages are with respect to ground (v ss ) unless otherwise stated. characteristics sym. min. typ. * max. units test conditions 1 i n p u t s input voltage (l in) v in 5.0 v pp 2 input impedance (l in )z in 20 k ? f baud =160 khz 3 crystal/clock frequency f c 10.24 mhz 4 crystal/clock tolerance t c -100 0 +100 ppm 5a crystal/clock duty cycle 1 dc c 40 50 60 % normal temp. & v dd 5b crystal/clock duty cycle 1 dc c 45 50 55 % recommended at max./ min. temp. & v dd 6 crystal/clock loading c l 33 50 pf from osc1 & osc2 to v ss . 7 o u t p u t s output capacitance (l out )c o 8pf 8 load resistance (l out ) (v bias , v ref ) r lout 500 100 ? k ? 9 load capacitance (l out ) (v bias , v ref ) c lout 0.1 20 pf f capacitance to v bias . 10 output voltage (l out )v o 3.2 4.3 4.6 v pp r lout = 500 ? , c lout = 20 pf ac electrical characteristics ? - clock timing - dn mode (figures 16 & 17) characteristics sym. min. typ.* max. units test conditions 1c4 clock period t c4p 244 ns 2c4 clock width high or low t c4w 122 ns in master mode - note 1 3 frame pulse setup time t f0s 50 ns 4frame pulse hold time t f0h 50 ns 5frame pulse width t f0w 244 ns 6 10.24 mhz clock jitter (wrt c4 )j c 15 ns note 2 channel 31 bit 0 channel 0 bit 7 channel 0 bit 6 f0 c4 st-bus bit cells
mt9173/74 data sheet 20 zarlink semiconductor inc. figure 16 - c4 clock & frame pulse alignment for st-bus streams in dn mode figure 17 - frequency locking for the c4 and osc1 clocks in mas/dn mode ? timing is over recommended temperature & power supply voltage ranges. * typical figures are at 25 c, for design aid only: not guaranteed and not subject to production testing. ac electrical characteristics ? - clock timing - mod mode (figure 18) characteristics sym 80 kbit/s 160 kbit/s units test conditions min. typ.* max. min. typ.* max. 1tck /rck clock period t cp 12.5 6.25 s 2 tck /rck clock width t cw 6.25 3.125 s 3 tck /rck clock transition time t ct 20 20 sc l =40 pf 4cld to tck setup time t clds 3.125 1.56 s 5cld to tck hold time t cldh 3.125 1.56 s 6cld width low t cldw 6.05 2.925 s 7cld period t cldp 8 x t cp 8 x t cp s c4 f0 2.0 v 0.8 v 2.0 v 0.8 v t c4p t c4w t f0s t f0h t f0w t c4w c4 osc1 2.0 v 0.8 v 3.0 v 2.0 v j c f
mt9173/74 data sheet 21 zarlink semiconductor inc. figure 18 - rck , tck & cld timing for mod mode ? timing is over recommended temperature & power supply voltage ranges. figure 19 - data timing for dn mode ac electrical ch aracteristics ? - data timing - dn mode (figure 19) characteristics sym. min. typ. max. units test conditions 1 dsti/cdsti data setup time t rs 30 ns 2 dsti/cdsti data hold time t rh 50 ns 3a dsto/cdsto data delay t td 120 ns c l =40 pf 3b dsto/cdsto high z to data delay t ztd 140 ns c l =40 pf rck tck cld t ct t cp t clds t cldh t cw t ct t cldw t cw 2.4 v 0.4 v 2.4 v 0.4 v 2.4 v 0.4 v t cp note 1: tck and cld are generated on chip and provide the data clocks for the cd port and the transmit section of the dv port. rck , also generated on chip, is extracted from the receive data and only clocks out the data at the d o output and may be skewed with respect to tck due to end-to-end delay. note 2: at the slave end tck is phase locked to rck . the rising edge of tck will lead the rising edge of rck by approximately 90 o . 2.0 v 0.8 v 2.4 v 0.4 v 2.0 v 0.8 v bit stream c4 dsti cdsti dsto cdsto bit cell t td t rs t rh t td t ztd
mt9173/74 data sheet 22 zarlink semiconductor inc. ? timing is over recommended temperature & power supply voltage ranges. * typical figures are at 25 c, for design aid only: not guaranteed and not subject to production testing. note 1 : attenuation measured from master l out to slave l in at 3/4baud frequency. * typical figures are at 25 c, for design aid only: not guaranteed and not subject to production testing. ac electrical characteristics ? - data timing - mod mode (figure 20) characteristics sym. 80 kbit/s 160 kbit/s units test conditions min. typ.* max. min. typ.* max. 1 di/cdi data setup time t ds 150 150 ns 2 di/cdi data hold time t dh 4.5 2.5 s 3 do data delay time t rd 70 70 ns c l =40 pf 4 cdo data delay time t td 70 70 ns c l =40 pf performance characteristics of the mt9173 dsic characteristics sym. min. typ.* max. units test conditions 1 allowable attenuation for bit error rate of 10 -6 (note 1) a fb 03025dbsnr 16.5 db (300 khz bandlimited noise) 2 line length at 80 kbit/s -24 awg -26 awg l 80 3.0 2.2 km attenuation - 6.9 db/km attenuation - 10.0 db/km 3 line length at 160 kbit/s -24 awg -26 awg l 160 3.0 2.2 km attenuation - 8.0 db/km attenuation - 11.5 db/km performance characteristics of the mt9174 dnic characteristics sym. min. typ.* max. units test conditions 1 allowable attenuation for bit error rate of 10 -6 (note 1) a fb 04033dbsnr 16.5 db (300 khz bandlimited noise) 2 line length at 80 kbit/s -24 awg -26 awg l 80 5.0 3.4 km attenuation - 6.9 db/km attenuation - 10.0 db/km 3 line length at 160 kbit/s -24 awg -26 awg l 160 4.0 3.0 km attenuation - 8.0 db/km attenuation - 11.5 db/km
mt9173/74 data sheet 23 zarlink semiconductor inc. figure 20 - data timing for master modem mode tx bit stream tck di cdi cdo rx bit stream do 2.4 v 0.4 v 2.0 v 0.8 v 2.4 v 0.4 v 2.4 v 0.4 v bit cell t ds t dh t td t td t rd t rd bit cell rck
mt9173/74 data sheet 24 zarlink semiconductor inc. figure 21 - data timing for slave modem mode figure 22 - rxsb timing for dn mas mode ac electrical characteristics ? - rxsb timing - dn mas mode (figure 22) * typical figures are at 25 c, for design aid only: not guaranteed and not subject to production testing. characteristics sym. min. typ.* max. units test conditions 1 rxsb delay t rxd 81.4 us 0 km, 160 kb 35.8 us 0 km, 80 kb 126 us 4 km, 24 awg, 160 kb 85 us 4 km, 26 awg, 80 kb tck di cdi cdo do 2.4 v 0.4 v 2.0 v 0.8 v 2.4 v 0.4 v 2.4 v 0.4 v t ds t dh t td t td rck ? t cp f0 rxsb t rxd
c zarlink semiconductor 2003 all rights reserved. apprd. issue date acn previous package codes: package code e1 pin 1 e d a2 a a1 e b b1 d1 l eb c d2

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